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1 typical application features description 3a monolithic buck-boost supercapacitor charger and balancer with accurate input current limit the lt c ? 3128 is a highly efficient, buck-boost dc/dc supercapacitor charger. it operates efficiently from input voltages above, below or equal to the output voltage. the ltc3128 incorporates accurate programmable average input current limit, active charge balancing and program - mable maximum capacitor voltage. this combination of features makes the l tc3128 ideal for safely charging and protecting large capacitors in backup power systems. the input current limit and maximum capacitor voltage are each programmed using a single resistor. average input current is accurately controlled over a 0.5a to 3a programmable range while the individual maximum capacitor voltage can be set from 1.8v to 3.0v. other features of the ltc3128 include <2a quiescent current from v out in burst mode ? operation, accurate power-good and power failure indicators, and thermal overload protection. the ltc3128 is offered in low profile, thermally enhanced 20-lead 4mm 5mm 0.75mm qfn and 24-lead tssop packages. wide v in (3a programmed input current) to 4.2v stacked output capacitors charging waveform applications n 2% accurate average input current limit programmable up to 3a n programmable maximum capacitor voltage limit n active charge balancing for fast charging of unmatched capacitors n charges single or stacked capacitors n v in range: 1.73v to 5.5v n v out range: 1.8v to 5.5v n <2a quiescent current from v out when charged n output disconnect in shutdown: <1a i q shutdown n power-good comparator n power failure indicator n thermally enhanced 20-lead (4mm 5mm 0.75mm) qfn and 24-lead tssop packages n supercapacitor based backup power n memory backup n servers, raid, rf systems n industrial, communications, computing l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 1.7v to 5.5v up to 3.0a 10f 127k 3.3h c1: murata dmf3z5r5h474m3dta0 301k 1.87m c1 c1b 940mf v out = 4.2v 3.57k c1a 940mf 10f sw1 rsenp rsens run pfi pfo pgood maxv gnd fb prog mid ltc3128 sw2 v outp v outs v in 3128 ta01 470pf v out 2.0v/div mid 2.0v/div i in 2.0a/div i load 2.0a/div 2 seconds/div 3128 ta01b ltc3128 3128f for more information www.linear.com/ltc3128
2 20 19 18 17 7 8 top view 21 gnd ufd package 20-lead (4mm 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 sw1 rsenp rsens run prog nc v outp v outp v outs mid pgood fb nc sw1 sw2 sw2 v in pfo pfi maxv t jmax = 125c, ja = 43c/w exposed pad (pin 21) is gnd, must be soldered to pcb (note 5) 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic tssop 24 23 22 21 20 19 18 17 16 15 14 13 sw1 gnd gnd sw1 rsenp rsens run prog nc nc v in gnd sw2 sw2 nc v outp v outp v outs mid pgood fb maxv pfi pfo 25 gnd t jmax = 125c, ja = 38c/w exposed pad (pin 25) should be soldered to pcb (note 5) pin configuration absolute maximum ratings v in , rsenp, v outp , mid voltage .................. C0 .3v to 6v rsens, v outs voltage ................................. C 0.3v to 6v rsens dc current .................................................... C 4a sw1, sw2 dc voltage ................................. C 0.3v to 6v sw1, sw2 pulsed (<100ns) voltage ............. C 1.0v to 7v pgood, pfo , run voltage .......................... C 0.3v to 6v (note 1) order information prog, maxv, fb, pfi voltage ..................... C0 .3v to 6v pgood, pfo dc current ........................................ 15 ma operating junction temperature range (notes 2, 4) ............................................ C 40c to 125c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) fe o nly ............................................................. 3 00c lead free finish tape and reel part marking package description temperature range ltc3128eufd#pbf ltc3128eufd#trpbf 3128 20-lead (4mm 5mm) plastic qfn C40c to 125c ltc3128iufd#pbf ltc3128iufd#trpbf 3128 20-lead (4mm 5mm) plastic qfn C40c to 125c ltc3128efe#pbf ltc3128efe#trpbf ltc3128fe 24-lead plastic tssop C40c to 125c ltc3128ife#pbf ltc3128ife#trpbf ltc3128fe 24-lead plastic tssop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www .linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc3128 3128f for more information www.linear.com/ltc3128
3 electrical characteristics parameter conditions min typ max units input operating range l 1.73 5.5 v programmed output voltage range l 1.8 5. 5 v fb voltage l 0.565 0.580 0.590 v fb voltage hysteresis 8.5 mv fb input current fb > 0.590v 0.5 2 na switching frequency while charging l 1.00 1.20 1.40 mhz power good rising threshold voltage measured as a % of fb voltage l 94.50 96.75 99.00 %fb power good hysteresis measured as a % of fb voltage 3.6 % power good voltage low i pgood = 5ma 200 mv power good leakage current pgood = 5.5v 0.1 1 a pfi falling threshold l 0.565 0.580 0.590 v pfi hysteresis current v pfi < 0.565v 0.2 a pfi input current v pfi > 0.590v 0.5 2 na pfo voltage low i pfo = 5ma 200 mv pfo leakage current pfo = 5.5v 0.1 1 a maximum capacitor voltage C rising r maxv = 125k, C40c to 125c (note 7) r maxv = 125k, 0c to 85c (notes 6, 7) r maxv = 113k, C40c to 125c (note 7) r maxv = 113k, 0c to 85c (notes 6, 7) l l l l 2.350 2.400 2.150 2.170 2.500 2.500 2.260 2.260 2.650 2.600 2.380 2.350 v v v v maximum capacitor v oltage hysteresis 120 200 mv maxv pin current 20 a v in quiescent current C sleep v run = 3.3v, v fb > 0.590v 14 a v out quiescent current C sleep v run = 3.3v, not balancing, v fb > 0.590v v run = 3.3v, balancing, v fb > 0.590v 1.9 100 a a v in quiescent current C shutdown v run = 0v, not including sw leakage 0.6 1 a v out quiescent current C shutdown v run = 0v, not including sw leakage 0.4 1 a v out quiescent current C shutdown v run = 0v, v in = 0v, not including sw leakage 0.4 1 a v in quiescent current C active v run = 3.3v (note 3) 600 a v in quiescent current C uvlo v run = 1.5v, v in = 1.5v, not including sw leakage 25 a v out quiescent current C uvlo v run = 1.5v, v in = 1.5v, not including sw leakage 1 2 a input current limit r prog = 22.1k (notes 3, 7) r prog = 22.1k (notes 3, 7) r prog = 11k (notes 3, 7) r prog = 11k (notes 3, 7) r prog = 5.49k (notes 3, 7) r prog = 5.49k (notes 3, 7) r prog = 3.57k (notes 3, 7) r prog = 3.57k (notes 3, 7) l l l l 489 475 985 958 1973 1923 3034 2951 497 497 1000 1000 2003 2003 3081 3081 504 515 1015 1035 2033 2075 3127 3185 ma ma ma ma ma ma ma ma the l denotes specifications that apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 3.3v, v out = 4.8v, unless otherwise noted. ltc3128 3128f for more information www.linear.com/ltc3128
4 note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the ltc3128 is tested under pulsed load conditions such that t j t a . the ltc3128e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3128i is guaranteed over the full C40c to 125c operating junction temperature range. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) according to the formula: t j = t a + (p d ? ja c/w), where ja is the package thermal impedance. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3. current measurements are made when the output is not switching. note 4. this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. note 5. failure to solder the exposed backside of the package to the pc board ground plane will result in a thermal resistance much higher than 43c/w in the qfn and 38c/w in the tssop. note 6. guaranteed by design. not tested. note 7. accuracy of this specification is directly related to the accuracy of the resistor used to program the parameter. parameter conditions min typ max units prog pin gain measured at i in = 1a (note 3) 52.7 a/a internal sense resistor value (note 6) 50 m peak inductor current limit (note 3) l 5.50 6.5 9.00 a linear inductor current limit (note 3) l 4.00 5.0 6.85 a n-channel mosfet leakage switches b and c and e 0.1 5 a p-channel mosfet leakage switches a and d switch f 0.1 0.1 5 10 a a n-channel mosfet on-resistance switch b switch c switch e (v out = 0v) 70 80 95 m m m p-channel mosfet on-resistance switch a switch d switch f 45 40 300 m m m mid leakage current v mid = 0v, v in = 3.3v, v sw1 = 3.3v 0.1 10 a mid pin regulation v out = 4.8v l 2.304 2.400 2.496 v active charge balancer enable threshold |v out /2-v mid | 60 118 mv active charge balancer hysteresis 60 mv active charge balancer peak current (note 3) 400 ma active charge balancer valley current (note 3) 50 ma run input high threshold voltage l 1.2 v run input low threshold voltage l 0.3 v run input current run = 5.5v 0.01 1 a electrical characteristics the l denotes specifications that apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) v in = 3.3v, v out = 4.8v, unless otherwise noted. ltc3128 3128f for more information www.linear.com/ltc3128
5 typical performance characteristics efficiency vs v out (3.0a i in ) average input current limit vs temperature (normalized) efficiency vs v out (0.5a i in ) efficiency vs v out (1.0a i in ) efficiency vs v out (2.0a i in ) t a = 25c, unless otherwise noted. v out (v) 0.5 efficiency (%) 60 80 5.5 3128 g01 40 1.5 3.5 4.5 1 32.52 4 5 100 50 70 90 v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v v in = 1.7v v out (v) 0.5 efficiency (%) 60 80 5.5 3128 g02 40 30 1.5 3.5 4.5 1 32.52 4 5 100 50 70 90 v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v v in = 1.7v v out (v) 0.5 efficiency (%) 60 80 5.5 3128 g03 40 30 20 10 0 1.5 3.5 4.5 1 32.52 4 5 100 50 70 90 v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v v out (v) 0.5 efficiency (%) 60 5.5 3128 g04 40 30 20 10 0 1.5 3.5 4.5 1 32.52 4 5 90 50 70 80 v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v ?45 normalized average input current (%) ?0.5 0 3128 g05 ?2.0 temperature (c) 55 95 ?25 3515?5 75 115 1.0 ?1.0 ?1.5 0.5 v out vs charge time, c out = 1f, r esr = 20m, i in = 0.5a v out vs charge time, c out = 1f, r esr = 20m, i in = 1.0a v out vs charge time, c out = 1f, r esr = 20m, i in = 2.0a v out vs charge time, c out = 1f, r esr = 20m, i in = 3.0a 0 v out (v) 3.5 3.0 2.5 3128 g21 0 10 12 14 16 18 20 22 24 2 84 6 5.5 5.0 2.0 1.5 1.0 0.5 4.5 4.0 time (s) v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v v in = 1.7v 0 v out (v) 3.5 3.0 2.5 3128 g22 0 6 7 8 9 10 11 12 13 14 15 1 52 3 4 5.5 5.0 2.0 1.5 1.0 0.5 4.5 4.0 time (s) v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v v in = 1.7v 0 v out (v) 3.5 3.0 2.5 3128 g23 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.00.5 5.5 5.0 2.0 1.5 1.0 0.5 4.5 4.0 time (s) v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v 0 v out (v) 3.5 3.0 2.5 3128 g24 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.00.5 5.5 5.0 2.0 1.5 1.0 0.5 4.5 4.0 time (s) v in = 5.0v v in = 4.2v v in = 3.3v v in = 2.4v ltc3128 3128f for more information www.linear.com/ltc3128
6 typical performance characteristics feedback voltage vs temperature (normalized) pfi voltage vs temperature (normalized) pfo pull down resistance vs v in pgood threshold vs temperature (normalized) pgood pull down resistance vs v in t a = 25c, unless otherwise noted. ?45 normalized feedback voltage (%) 0.20 0.25 3128 g10 0.35 55 95 ?25 3515?5 75 115 0.00 0.05 0.30 0.10 0.15 temperature (c) ?45 normalized pfi voltage (%) ?0.15 ?0.20 3128 g11 ?0.40 55 95 ?25 3515?5 75 115 0.05 0.00 ?0.25 ?0.30 ?0.35 ?0.05 ?0.10 temperature (c) 1.7 resistance () 40 30 3128 g12 0 3.7 4.5 4.9 2.1 3.32.92.5 4.1 5.3 90 60 70 80 20 10 50 v in (v) ?45 normalized pgood threshold (%) ?0.15 ?0.20 3128 g13 ?0.35 55 95 ?25 3515?5 75 115 0.00 ?0.05 ?0.25 ?0.30 ?0.10 temperature (c) 1.7 resistance () 60 50 3128 g14 0 3.7 4.5 2.1 3.32.92.5 4.1 4.9 5.3 90 80 40 30 20 10 70 v in (v) maximum programmable i in vs v in v in quiescent current vs v in (burst mode operation sleep) v in quiescent current vs v in (input uvlo) v out quiescent current vs v out (burst mode operation sleep) 1.7 i in (a) 2.25 2.75 3128 g06 1.75 v in (v) 3.7 4.5 2.1 3.32.92.5 4.1 4.9 5.3 3.25 2.00 2.5 3.00 1.7 input current (a) 12.2 12.0 12.8 12.6 3128 g07 11.6 v in (v) 3.7 4.5 2.1 3.32.92.5 4.1 4.9 5.3 13.6 13.4 11.8 12.4 13.2 13.0 0 input current (a) 5.00 20.0 15.0 3128 g08 0.00 v in (v) 1.0 1.4 0.2 0.80.60.4 1.2 1.6 1.8 40.0 35.0 10.0 30.0 25.0 1.8 output current (a) 1.1 1.0 1.4 1.3 3128 g09 0.9 3.8 4.6 2.2 3.43.02.6 4.2 5.0 5.4 1.8 1.7 1.2 1.6 1.5 v out (v) ltc3128 3128f for more information www.linear.com/ltc3128
7 typical performance characteristics minimum and maximum programmed capacitor voltage vs programmed v out startup waveform 1.0a input current limit maximum capacitor voltage vs temperature (normalized) t a = 25c, unless otherwise noted. startup waveform 3.0a input current limit ?45 normalized maximum capacitor voltage (%) 2.0 3128 g15 ?0.8 55 95 ?25 3515?5 75 115 0.8 0.6 0 ?0.2 ?0.4 ?0.6 0.4 temperature (c) 5.00s/div v out 2v/div v mid 2v/div i in 0.5a/div run 5v/div 3128 g17 5.00s/div i in 2a/div v out 2v/div v mid 5v/div 3128 g18 v out (v) 2.7 3.1 3.5 8.9 4.3 4.7 5.1 programmed maxv (v) 3 5.5 3128 g16 1 0 6 2 4 minimum (?40c to 125c) minimum (0c to 85c) 5 maximum ltc3128 3128f for more information www.linear.com/ltc3128
8 pin functions sw1 (pins 1, 19/pins 1, 4): switch pin where internal switches a and b are connected. connect an inductor from sw1 to sw2. rsenp (pin 2/pin 5): sense resistor power output. connect other loads in the system to this pin. a 10f or greater ceramic capacitor should be placed as close to rsenp and gnd as possible. rsens (pin 3/pin 6): sense resistor signal input. this pin should be connected to rsenp through as short and wide a trace as possible. run (pin 4/pin 7): logic-controlled shutdown input. run 1.2v: normal operation run 0.3v: shutdown prog (pin 5/pin 8): sets the average input current limit threshold. connect a resistor and capacitor from prog to gnd. see below for component value selection. r prog (k) = 11/i limit (a) c prog (pf) = 1600/(r prog (k)) nc (pins 6, 20/pins 9, 10, 22): not connected. these pins should be tied to ground. v in (pin 7/pin 11): input supply pin. internal v cc for the ic and high current input to the internal sense resistor. a 10f or greater ceramic capacitor should be placed as close to v in and gnd as possible. pfo (pin 8/pin 13): power fail output. this is an open- drain output that sinks current when the supply being monitored is less than the programmed threshold voltage. pfi (pin 9/pin 14): power fail input. connect resistor divider tap from supply to be monitored here. see below for component selection. v pfi(falling) (v) = 0.58 ? (1+r4/r3) v pfihyst (v) = r4 ? 0.2a maxv (pin 10/pin 15): sets the maximum capacitor voltage across each capacitor. connect a resistor from maxv to gnd. see below for component value selection. if charging only a single capacitor, tie this pin to ground. r maxv (k) = 50 ? v maxv (v) fb (pin 11/pin 16): output voltage feedback pin. connect resistor divider tap here. the output voltage can be adjusted from 1.8v to 5.5v. the feedback reference voltage is 0.58v. v out (v) = 0.58 ? (1+r2/r1) pgood (pin 12/pin 17): power good indicator. this is an open-drain output that pulls low when v out is less than 96.75% of the programmed voltage. mid (pin 13/pin 18): output for the active charger balancer. this pin should be tied to the junction of the two output capacitors. if charging only a single output capacitor, tie this pin to ground as shown in the applications section. v outs (pin 14/pin 19): output sense input. this pin should be connected to the v out capacitor through as short a trace as possible. v outp (pins 15,16/pins 20, 21): output of the synchro - nous rectifier. connect the output filter capacitor from this pin to gnd. see the applications information section for capacitor recommendations. sw2 (pins 17,18/pins 23, 24): switch pin where internal switches c and d are connected. connect inductor from sw1 to sw2. gnd (exposed pad pin 21/pins 2, 3, 12 exposed pad pin 25): ic and power ground. the exposed pad must be soldered to the pcb ground plane through a good electrical and thermal connection. (qfn/tssop) ltc3128 3128f for more information www.linear.com/ltc3128
9 block diagram v in prog run r4 r3 pfi 0.58v 6.5a pgood 0.58v 0.2a gnd pfo v outp v outs sw1 0.56v maxv 3128 bd v out mid mid sw1 rsens rsenp sw2 d a b c e peak amp ilinear amp zero amp ? + ? + ? + 0.58v 20a ? + + ? + ? 0.56v fb logic balancer logic + ? + ? fb f + ? + ? + ? + ? r2 r1 a=1 a=1 5a ltc3128 3128f for more information www.linear.com/ltc3128
10 operation the ltc3128 is an average input current controlled buck- boost dc/dc charger offered in both a thermally enhanced 4mm 5mm 20-lead qfn package and a thermally en - hanced 24-lead tssop package. the buck-boost charger utilizes a proprietary switching algorithm which allows its output to be regulated above, below , or equal to the input voltage. the low r ds(on) , low gate charge synchronous switches provide high efficiency conversion to minimize the charging time of storage elements. charger operation the ltc3128 uses fixed frequency, average input current pwm control when charging the output capacitor(s). a proprietary switching algorithm allows the charger to switch between buck and boost modes without discontinu - ity in inductor current or loop characteristics. the switch topology for the buck-boost charger is shown in figure 1. t wo switches (d and e) connect sw2 to v out to provide high efficiency over the entire output voltage range. as the input voltage decreases further, switch pair cd is pulse width modulated to obtain the desired output voltage. at this point, the converter is operating solely in boost mode. when v out is below 1.5v typical, switch d and e are modulated. this helps to improve efficiency at low v out voltages. this switching algorithm provides a seamless transition between operating modes and eliminates discontinuities in average inductor current, inductor current ripple, and loop transfer function throughout all operational modes. these advantages result in increased efficiency and stabil - ity in comparison to the traditional 4-switch buck-boost converter. error amplifier and compensation the ltc3128 utilizes two control loops. the hysteretic voltage loop determines whether the output is in regulation or not, and commands the ltc3128 into a low quiescent current sleep state when v out reaches its programmed level. the voltage loop is also equipped with a proportional gain control that reduces the charging current as v out approaches regulation. this helps prevent chattering into and out of sleep because of the large charging currents and possibly high equivalent series resistance (esr) ca - pacitors. the current loop is internally compensated and forces the input current to the programmed input current limit. when the l tc3128 is not sleeping or balancing, it operates at a fixed 1.2mhz frequency. current limit operation the ltc3128 has three current limit circuits. the primary current limit is an accurate average input current limit circuit that measures the input current drawn from the source by the ltc3128 and the other loads tied to the rsens pin via an internal 50m sense resistor. the ltc3128, when not sleeping, will always try to limit the input current passing through the sense resistor. any current drawn externally from rsens will result in a corresponding decrease in the charging current supplied by the ltc3128. if the load tied to rsens draws more than the programmed amount, the ltc3128 will reduce the charging current to zero, although it cannot limit the current draw from external sources. the l d e ltc3128 a sw1 sw2 b c 3128 f01 v out v in figure 1. buck-boost switch topology the ltc3128 uses a continuous switching algorithm where both sw1 and sw2 will switch regardless of the input or output. when the input voltage is significantly greater than the output voltage, the buck-boost converter oper - ates in buck mode. each cycle, switches b and c turn on for a minimum of 5% of the entire switching cycle. for the remainder of the switching cycle, switch d (switch d and e when v out <1.5v typically) turns on continuously, switch c remains off, and switches a and b are pulse width modulated to produce the required duty cycle to support the output regulation voltage. as the input volt - age decreases or as the output voltage increases, switch a remains on for a larger portion of the switching cycle. ltc3128 3128f for more information www.linear.com/ltc3128
11 input current limit is set by placing a resistor, r prog , from prog to gnd. this resistor and the c prog capacitor value can be calculated using the following formula: r prog (k) = 11/i limit (a) c prog (pf) 1600/(r prog (k) ) where i limit is the average input current limit in amps. a secondary linear current limit, limits the maximum aver - age inductor current to 5.0a typically. if the peak inductor current reaches 6.5a (typical) switches a and c are im - mediately turned off, and switches b and d are turned on. the linear and peak current limits are fixed and therefore are not affected by the value of r prog . zero current comparator the zero current comparator monitors the inductor current to the output and shuts off all power switches when this current reduces to approximately 30ma. this prevents the inductor current from reversing in polarity, improving efficiency at light loads. shutdown shutdown of the ltc3128 is accomplished by pulling the run pin below 0.3v and ic operation is enabled by pull - ing the run pin above 1.2v. note that run can be driven above v in or v out , as long as it is limited to less than the absolute maximum rating. thermal shutdown if the die temperature exceeds 165c (typical) the ltc3128 will be disabled. all power devices will be turned off and both switch nodes will be pulled low. the ltc3128 will restart (if enabled) when the die temperature drops to approximately 155c. thermal regulator to help prevent the part from going into thermal shut-down when charging very large capacitors at high current, the ltc3128 is equipped with a thermal regulator. if the die temperature exceeds 135c (typical) the average current limit is lowered to help reduce the amount of power being operation dissipated in the package. the current limit will continue to be reduced to approximately 30% of the programmed limit just before thermal shutdown. the current limit will return to its full value when the die temperature drops below 135c. see the pcb layout considerations section in the applications information portion of the data sheet for additional thermal considerations. undervoltage lockout if the input supply voltage drops below 1.60v (typical), the ltc3128 will be disabled and all power devices will be turned off. the ltc3128 will resume operation when v in rises above 1.73v. power failure indicator the ltc3128 includes a power failure indicator comparator. referring to the block diagram, the non-inverting input of the comparator is internally connected to a 0.58v reference and the inverting input is connected to the pfi pin. an external resistive divider can be placed from the supply being monitored to ground to program the thresh - old voltage. when the voltage at pfi drops below 0.58v, the open-drain n-channel mosfet on pfo will turn on, pulling the pin low. the n-channel mosfet is forced off when the ltc3128 is in shutdown. when pfi drops below 0.58v, a hysteresis current of 0.2a will turn on, sinking current into the pfi pin providing hysteresis. once the pfi pin rises above 0.58v plus the programmed hysteresis, the open-drain n-channel mosfet on pfo will turn off. the power failure indicator voltage and hysteresis can be calculated as follows: v pfi(falling) (v) = 0.58 ? (1 + r4/r3) v pfihyst (v) = r4 ? 0.2a power-good indicator the ltc3128 includes a power-good indicator comparator. the non-inverting input of the comparator is connected to the fb pin and the inverting input is internally connected to a 0.56v reference. when the voltage at fb drops below approximately 0.54v, the open-drain n-channel mosfet on pgood will turn on, pulling the pin low. the n-channel mosfet is forced off when the ltc3128 is in shutdown. ltc3128 3128f for more information www.linear.com/ltc3128
12 operation maximum capacitor voltage comparator the ltc3128 monitors the voltage across each capacitor of the stacked output capacitors. if a capacitor exceeds the programmed maximum capacitor voltage, the ltc3128 will stop charging the output stack and begin balancing the voltage on the two capacitors. if the capacitors cannot be balanced and the fault condition still persists, charging will be halted until the output capacitors self discharge so that a fault condition no longer exists. this condition can exist if there is a shorted or damaged output capacitor. the maximum capacitor voltage is programmed by placing a single resistor from maxv to gnd. the r maxv resistor should be placed close to the maxv pin to minimize the pin capacitance. the typical resistor value can be calculated using the following formula: r maxv (k) = 50 ? v maxv (v) where v maxv is the maximum allowable voltage across a capacitor. with the calculated r maxv value, the observed v maxv can vary as much as 6%. the maximum capacitor voltage comparator is not enabled until v out is greater than approximately 1.5v. if the maxv pin is tied to ground, both the maximum capacitor voltage comparator and the active charge balancer are disabled. the maxv pin should be tied to ground if only a single output capaci - tor is being charged and no balancing is required. when using a single capacitor , the maximum capacitor voltage is programmed using the fb pin. the voltage loop will prevent over voltaging of the output capacitor, and the mid pin should be grounded. please refer to the typical applications section for an example. active charge balancer the ltc3128 includes an active charge balancer for the stacked output capacitors. the balancer efficiently moves charge from the overcharged capacitor to the undercharged capacitor until the two capacitors are determined to be balanced. this helps to ensure the long term reliability of the capacitors by insuring one-half of the programmed output voltage is across each capacitor and eliminates the need for lossy balancing resistors or shunt regulators. the active charge balancer is enabled once the voltage on the mid pin exceeds approximately 1.2v. the ltc3128 will try to balance the stack only if v out has reached regula - tion, or if one of the capacitor voltages has exceeded the maximum progra mme d value. this ensures that the output stack is charged as quickly as possible while protecting each capacitor from being overcharged. the balancer is hysteretic and is enabled once the two capacitors are 60mv out of balance. once the balancer has equalized the voltage across each capacitor, it is disabled. the active charge balancer operates by using the induc - tor connected between sw1 and sw2 to efficiently move charge between the two output capacitors. the charge is moved through a switch that connects the mid pin to sw1 internally . connecting the mid pin to sw1 allows the l tc3128 to either boost charge from the bottom capaci - tor to the top, or buck charge from the top capacitor by modulating switches c and d. if v mid is 60mv greater than v out C v mid switches c and f are turned on until the inductor current reaches 400ma. switch c is then turned off and switch d is turned on until the inductor current reaches 50ma. this switching cycle continues until v mid = v out C v mid . if v out C v mid is 60mv greater than v mid , switches d and f are turned on until the inductor current reaches C400ma. switch d is then turned off and switch c is turned on until the inductor current reaches C50ma. the switching cycle continues until v mid = v out C v mid . the frequency that the balancer will operate at is dependent on the inductor value (l) and can be calculated by: f balancer (mhz) v out 1.6 ?l h ( ) ltc3128 3128f for more information www.linear.com/ltc3128
13 a typical ltc3128 application circuit is shown on the front page of this data sheet. the external component selection is determined by the desired output voltage, input cur - rent limit, maximum capacitor voltage, and v out ripple requirements for each particular application. however, basic guidelines and considerations for the design process are provided in this section. output voltage programming the output voltage is set by a resistive divider according to the formula: v out (v) = 0.58v ? (1 + r2/r1) the external divider is connected to the output as shown in figure 2. the ltc3128 buck-boost charger utilizes input current mode control, and the output divider resistance does not play a role in system stability. large resistor values can be used to minimize output leakage. the pro - grammed maximum capacitor voltage affects the maximum output voltage that can be programmed. this maximum programmed output voltage can be calculated by: v out(max) = 2 ? (v maxv C 440mv) (C40c to 125c) v out(max) = 2 ? (v maxv C 385mv) (0c to 85c) applications information ltc3128 gnd 1.8v v out 5.25v fb r1 3128 f02 r2 figure 2. setting the buck-boost output voltage less. the peak-to-peak inductor current ripple for buck and boost mode can be calculated from the following formulas, where l is the inductance in micro henries: ?i l,p ? p,buck (a) = v out (v in ? v out ) v in ? l ? 1.2 ?i l,p ? p,boost (a) = v in (v out ? v in ) v out ? l ? 1.2 the 1.2mhz switching frequency allows the ltc3128 to utilize small surface mount inductors. inductor values between 2.2h and 4.7h are recommended. these val - ues provide low ripple in the inductor current, but will not adversely affect the stability of the ltc3128. an inductor value that is too small or large will limit the stable input voltage range for a given v out . high frequency ferrite core inductor materials reduce frequency dependent power losses compared to cheaper powdered iron types, improving efficiency. the inductor should have low dc resistance (approximately 20m or less) to reduce the i 2 r power losses, and must be able to support the peak inductor current without saturating. molded chokes and chip inductors usually do not have enough core area to support the maximum peak inductor currents of up to 9.0a seen on the ltc3128. the inductor current can still reach currents greater than 5a even at low programmed input currents due to high voltage step-down ratios at start-up. see table 1 and the reference schematics for suggested components and suppliers. input capacitor selection the style and value of capacitors used with the ltc3128 determine input voltage ripple. it is required that a low equivalent series resistance (esr) multilayer ceramic capacitor of at least 10f be used to bypass the v in , rsens and rsenp pins. the value of the capacitor on v in directly controls the amount of input ripple for a given input current pulse, such as during a bucking switching cycle. increasing the value of this capacitor will reduce the input ripple. inductor selection to achieve high efficiency, a low dcr inductor should be utilized for the buck-boost charger. the inductor must have a saturation rating greater than the worst case average inductor current plus half the ripple current. this is due to the fact that during start-up or high step down ratios, the inductor current will be at the linear current limit (4.0a minimum) even if the programmed input current is ltc3128 3128f for more information www.linear.com/ltc3128
14 multilayer ceramic chip capacitors (mlcc) typically have exceptional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors available, each having considerably different characteristics. for example, x7r and x7s ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have higher packing density but poorer performance over their rated voltage and temperature ranges. y5v ceramic capacitors are not recommended because of their extreme non-linear characteristic of capacitance versus voltage and poor temperature stability. output capacitor selection the ltc3128 is designed to charge supercapacitors with a minimum total output capacitance value greater that 2mf. in general, lower capacitance capacitors have higher esrs. to prevent modulation in and out of sleep due to the volt - age step caused by capacitor esr, the ltc3128 reduces charge current in the last 5% of the v out charge cycle. at the end of the charging cycle immediately before sleep, the input current is reduced to 20% of the programmed value. also of importance is to try and minimize the droop due to the esr, and keep the droop less than 1% of the programmed output voltage. when the charging current is reduced to zero, the output voltage esr component is eliminated. the maximum recommended esr for the recommended 1% droop on v out is calculated by: (r esr1 + r esr2 )( ? ) ? v out 2 (20 ? v in ? i lim ? ) where r esr1 , r esr2 are the esr of each capacitor, v in is the input voltage to the charger, i lim is the programmed input current in amps, is the fractional efficiency of the charger at 20% of the programmed input current, and v out is the programmed output of the charger. if the esr of the capacitors is larger than this calculated value, some chattering in and out of sleep at the end of charge may be observed. figure 3 shows the voltage droop on v out caused when charging stops. the ltc3128 is stable with a total output capacitance value greater than 2mf, or 4mf for each stacked capacitor. supercapacitors are much larger physically than ceramic or tantalum capacitors, and therefore usually cannot be placed close to the charger. to minimize layout contribution to capacitor esr, the trace width connecting the capacitors to each other and the ic should be as large as possible. the mid pin trace is not as critical, as it only carries 200ma applications information table 1: recommended inductors vendor value (h) dcr (m) max dc current (a) size (mm) w l h coilcraft xal5030-222me xal5030-332me xal6030-332me xal6060-472me 2.2 3.3 3.3 4.7 13.2 21.2 19.9 13.1 9.2 8.7 12.2 10.5 5.0 5.0 3.0 5.0 5.0 3.0 6.0 6.0 3.0 6.0 6.0 6.0 coiltronics hc8-2r6-r hc8-3r5-r hc7-3r9-r hc7-4r7-r 2.6 3.5 3.9 4.7 11.4 16.5 7.9 9 10.2 8.5 10.4 9.2 10.9 10.9 4.0 10.9 10.9 4.0 13.0 13.8 5.5 13.0 13.8 5.5 sumida cdrh10d68rt125np-2r2nc cdrh10d38dhpnp-3r3pc cdrh127/hpnp-4r7rc 2.2 3.3 4.7 7.1 13.5 18.8 10.5 9.25 10.8 10.2 10.2 6.8 10.0 10.0 3.8 12.5 12.5 8.0 tdk vlf12060t-2r7n100 vlf12060t-3r9n9r0 2.7 3.9 5.3 7 10 9 11.7 12.0 6.0 11.7 12.0 6.0 wrth elektronik 744311220 744325420 2.2 4.2 11.4 7.1 9 11 6.9 7.0 3.8 10.2 10.5 4.7 ltc3128 3128f for more information www.linear.com/ltc3128
15 figure 3. v out voltage droop at end of charging applications information of average current during balancing, but the v out trace can carry more than 6a of current. it is recommended that local decoupling capacitors be placed from v out to mid and from mid to ground, as close to the ic as possible. multilayer ceramic capacitors are an excellent choice for output decoupling as they have extremely low esr and are available in small footprints. while a 10f decoupling capacitor is sufficient for most applications, larger values may be used without limitation. if using a single output capacitor, where balancing is not required, the maxv and the mid pin should be tied to ground, this prevents the ltc3128 from trying to balance. the hysteretic voltage loop of the ltc3128 will protect the output capacitor, by regulating it to the voltage programmed by the fb pin. pulsed output loads a large output capacitance can be used to help with pulsed load applications by reducing the amount of current re - quired by the ltc3128. the maximum load for a given pulsed load duty cycle and the minimum capacitance can be calculated by: i load(max) (a) = v in ?i lim ? d ? v out c out(min) (f) = i pulse C v in ?i lim ? v out Ci standby ? ? ? ? ? ? ? ? ? ? ? ? ? d ? t v droop where i standby is the continuous load current on the output in amps, i pulse is the pulsed load current in addition to i standby in amps, i lim is the programmed average cur - rent in amps, is the ltc3128 converter efficiency, d is the load pulse s duty cycle, and t is the period of the load pulse in seconds. when selecting output super capacitors for large pulsed loads, the magnitude and duration of the pulsed current, together with the droop voltage specifica - tion, determine the choice of the output capacitor. both the esr and the charge stored in the capacitors each cycle contribute to the output voltage droop. the droop due to the pulsed load and esr is calculated by: v droop,load (v) = i pulse C v in ?i lim ? v out Ci standby ? ? ? ? ? ? ? ? ? ? ? ? ?d ? t c out,total (f) v droop,esr (v) = i pulse C v in ?i lim ? v out Ci standby ? ? ? ? ? ? ? ? ? ? ? ? ? r esr1 + r esr2 ( ) where i standby is the continuous load current on the output in amps, i pulse is the pulsed load current in addi - tion to i standby in amps, i lim is the programmed average current in amps, d is the load pulses duty cycle, and t is the period of the load pulse in seconds. the total output voltage droop is given by: v droop (v) = v droop,load + v droop,esr low esr and high capacitance are critical to maintaining low output droop. table 2 and the typical applications schematics show supercapacitors that work well with the ltc3128. 1ms/div i in 500mv/div v out 10mv/div 3128 f03 ltc3128 3128f for more information www.linear.com/ltc3128
16 maximum capacitor voltage & balancing the service lifetime of a supercapacitor is determined by its rated voltage, rated temperature, rated lifetime, actual operating voltage, and operating temperature. to extend the life of a supercapacitor the operating voltage and temperature should be reduced from the maximum ratings. the websites for illinois capacitor 1 and maxwell 2 provide the means to determine their capacitor lifetime. using the suggested derated voltage for each capacitor will improve lifetime. the ltc3128 will keep each capacitor voltage at v out /2 once the output has reached regulation. to prevent an overvoltage on one of the output capacitors during charging, the maximum capacitor voltage compara - applications information tors continuously monitor the output stack. if a capacitor exceeds the programmed maximum capacitor voltage, the ltc3128 immediately stops charging the stack. if a capacitor exceeds its maximum voltage and the mid pin is greater than 1.2v, the ltc3128 will balance the voltage of the capacitors, otherwise the part will halt charging until the maximum capacitor voltage violation clears, typically by an external load or leakage. the ltc3128 will start balancing the stacked output capacitors if the output is in regulation and the two capacitors are more than 60mv out of balance, or any time a maximum voltage event occurs. how well the output capacitors are matched will determine the likelihood of triggering a maximum capacitor voltage fault during charging. the maximum capacitor voltage can only force the ltc3128 to stop charging and, depending on other conditions, attempt to balance the capacitors. note 1: http://www.illinoiscapacitor.com/tech-center/life-calculators.aspx note 2: http://www.maxwell.com/products/ultracapacitors/docs/ applicationnote1012839_1.pdf table 2: recommended supercapacitors and ultracapacitors vendor value (f) esr (m) vol t age (a) temperature range (c) size (mm) w l h murata electronics dmf3r5r5l334m3dta0 dmf3z5r5h474m3dta0 0.33 0.47 60 40 4.2 (5.5 peak) 4.2 (5.5 peak) C30 to 70 C30 to 70 14.0 21.0 2.5 14.0 21.0 3.2 t ecate tpl-10/10x30f tpl-25/16x26f tpl-100/22x45f tple-25/16x26f tple-100/22x45f tpls-400/35x60f 10 25 100 25 100 400 85 42 15 42 15 12 2.7 2.7 2.7 2.3 2.3 2.7 C40 to 65 C40 to 65 C40 to 65 C40 to 85 C40 to 85 C40 to 65 10.0 10.0 30.0 16.0 16.0 26.0 22.0 22.0 45.0 16.0 16.0 26.0 22.0 22.0 45.0 35.0 35.0 60.0 av x bz015a503z_b bz015a104z_b 0.05 0.1 160 80 5.5 5.5 C20 to 70 C20 to 70 28.0 17.0 4.1 28.0 17.0 6.7 cap-xx hs206f hs230 0.6 1.2 70 50 5.5 5.5 C40 to 85 C40 to 85 39.0 17.0 2.5 39.0 17.0 3.8 cooper bussmann a1635-2r5475-r m1325-2r5905-r hv1860-2r7107-r 4.7 9 100 25 20 10 2.5 2.5 2.7 C25 to 70 C40 to 60 C40 to 65 16.0 16.0 35.0 13.0 13.0 26.0 18.0 18.0 60.0 illinois capacitor 506der2r5slz 357der2r5sez 50 100 30 12 2.5 2.5 C40 to 70 C40 to 70 18.0 18.0 60.0 35.0 35.0 60.0 maxwell bcap0005 bcap0100t01 5 100 170 15 2.7 2.7 C40 to 65 C40 to 65 10.0 10.0 20.0 22.0 22.0 45.0 t aiyo y uden pas2026fr2r5504 pas0815ls2r5105 lic2540r3r8207 0.5 1 200 55 70 50 2.5 2.5 2.2 to 3.8 C25 to 60 C25 to 70 C25 to 70 26.0 20.0 0.9 8.0 8.0 15.0 25.0 25.0 40.0 ltc3128 3128f for more information www.linear.com/ltc3128
17 applications information the ltc3128 has minimal current draw from v out , es- pecially when the cells are in balance (typically < 2a). care should be taken to limit sour ces of current that may pull v out above its programmed regulation value, as there is no way for the ltc3128 to maintain regulation in this situation. if there is potential for external leakage to overvoltage the supercapacitors, measures should be taken to protect them. pcb layout considerations the ltc3128 switches large currents at high frequen - cies. special care should be given to the pcb layout to ensure stable, noise free operation. due to the high input and output power of the l tc3128 a four layer pcb with significant copper and ground planes is strongly recom - mended. other wise the thermal regulator may start to reduce the programmed input current at a lower ambient temperature, and may not be able to prevent the device from entering thermal shutdown. the l tc3128 evaluation board shows a recommended layout and part placement. figures 4 through 9 show the part placements and routing, a ltc3128 evaluation board is available on the linear technology website. the layout of the pcb and the amount of copper used directly effects the ja of the ltc3128. the ja of the ltc3128 on the evaluation board layout shown is 20c/w. if thinner copper, less copper area, or fewer vias are used then this number will increase. the following items provide guidelines for layout of the ltc3128: 1. use solid ground plane under the whole circuit (no other traces underneath) 2. place all decoupling capacitors close to ltc3128 (that ensures low parasitic inductances) 3. use 2 to 3 local ground vias next to the gnd pad of each decoupling capacitor. 4. place the maximum number of gnd vias under the exposed pad of ltc3128 (for low thermal resistance) 5. place a local gnd via next to each component that is connected to ground. 6. keep fb and maxv nodes short (place the voltage divider resistors close to the pins) the l tc3128 is equipped with a thermal regulator that is designed to help protect the ltc3128 from damage due to overheating. the thermal regulator will try to prevent the die temperature from exceeding 135c by reducing the input current limit, but if it cannot, the ltc3128 will eventually enter thermal shutdown at 165c. when the junction temperature of the ltc3128 drops back below 135c the input current limit will no longer be affected. figure 4. ltc3128 evaluation board top side silkscreen figure 5. ltc3128 evaluation board top metal ltc3128 3128f for more information www.linear.com/ltc3128
18 applications information figure 6. ltc3128 evaluation board layer 2 metal figure 7. ltc3128 evaluation board layer 3 metal figure 8. ltc3128 evaluation board back side metal figure 9. ltc3128 evaluation board back side silkscreen ltc3128 3128f for more information www.linear.com/ltc3128
19 typical applications usb 3.0 (900ma programmed input current) powered, 4.8v backup supply usb 3.0 4.5v to 5.5v 900m a 10f 142k 3.3h 301k 2.21m v out = 4.8v maxv = 2.85v 130pf 300f 300f to load 10f sw1 rsenp rsens run pfi pfo pgood maxv gnd fb prog mid ltc3128 sw2 v outp v outs v in 3128 ta02 12.4k 10f 10f v out 1v/div mid 1v/div i in 500ma/div 200 seconds/div 3128 ta02b ltc3128 3128f for more information www.linear.com/ltc3128
20 typical applications 5.0v to 3.3v converter with power ride-through v in 5.0v 3.0a 10f 10f 470pf 0.1f 47f 22f 2 3300pf 200f 200f 3128 ta04 sw1 rsenp rsens run pfi pfo pgood maxv gnd fb prog mid ltc3128 sw2 v outp v outs v in 3.3h 147k 3.57k 2.32m 301k 60.4k 47k 316k 182k v out = 5.0v ena gnd enb ina outa inb outb stat control circuit ltc4413 4.7h sw1 mode v in shdn prog sgnd pgnd fb sw2 v out v c ltc3127 33pf v out = 3.3v to load 1.8v to 5.5v input buck-boost converter this circuit will provide the 3.3v output while supercapacitors are discharging from 5v down to 1.8v. the large delta from 5v down to 1.8v allows 87% of stored energy in the supercapacitors to be utilized 10f 10f v out 5.0v/div ltc3128 v out 5.0v/div ltc3127 v out 2.0v/div ltc3128 i in 2.0a/div 200 seconds/div 3128 ta04b ltc3128 3128f for more information www.linear.com/ltc3128
21 typical applications supercapacitor backup with secondary converters (3a programmed input current) li-ion 2.8v to 4.2v 3.0a 10f 142k 3.3h 301k 2.21m 400f v out = 4.8v 470pf 400f to load 10f sw1 rsenp rsens run pfi pfo pgood maxv gnd fb prog mid ltc3128 sw2 v outp v outs v in 3128 ta03 3.57k 2.0m 499k to main system loads, 3a maximum p this supercapacitor backup circuit will draw only the current that is left over from the 3a of input current consumed by main loads in the system 10f 10f ltc3128 3128f for more information www.linear.com/ltc3128
22 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 1.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd20) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.65 0.05 2.50 ref 4.10 0.05 5.50 0.05 1.50 ref 3.10 0.05 4.50 0.05 package outline r = 0.05 typ 2.65 0.10 3.65 0.10 3.65 0.05 0.50 bsc ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) ltc3128 3128f for more information www.linear.com/ltc3128
23 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe24 (aa) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 7.70 ? 7.90* (.303 ? .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev b) exposed pad variation aa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. ltc3128 3128f for more information www.linear.com/ltc3128
24 related parts typical application part number description comments ltc3225/ltc3225-1 150ma supercapacitor charger low noise, constant frequency charging of two series supercapacitors. automatic cell balancing prevents capacitor overvoltage during charging. programmable charge current (up to 150ma). selectable 2.4v or 2.65v regulation per cell (ltc3225), selectable 2v or 2.25v regulation per cell (ltc3225-1). 2mm 3mm dfn package ltc3226 2-cell supercapacitor charger with backup powerpath? controller 1/2 multimode charger with automatic cell balancing. internal 2 a ldo backup supply. 16 lead 3mm 3mm qfn package ltc3625/ltc3625-1 1a high efficiency 2-cell supercapacitor charger with automatic cell balancing high efficiency step-up/step-down charging of two series supercapacitors. automatic cell balancing prevents capacitor overvoltage during charging. programmable charging current up to 500ma (single inductor), 1a (dual inductor). v in = 2.7v to 5.5v, selectable 2.4v/2.65v regulation per cell (ltc3625). selectable 2v/2.25v regulation per cell (ltc3625-1), low no-load quiescent current: 23a. 12-lead 3mm 4mm dfn package ltc3606b 800ma i out , synchronous step-down dc/dc converter with average input current limit 95% efficiency, v in : 2.5v to 5.5v, v out(max) = 0.6v, i q = 420a, i sd < 1a, 3mm 3mm dfn-8 package l tc4425 super capacitor charger with current limited ideal diode constant-current/constant-voltage linear charger for 2-cell series supercapacitor stack. v in : li-ion/polymer battery, a usb port, or a 2.7v to 5.5v current-limited supply. 2a charge current, auto cell balancing, 20a quiescent current, shutdown current < 2a. low profile 12-pin 3mm 3mm dfn or a 12-lead msop packages ltc3127 1a buck-boost converter with programmable input current limit 96% efficiency, 4% accurate average input current limit, v in : 1.8v to 5.5v, v out = 1.8v to 5.25v, i q = 35a, dfn package ltc3125 1.2a i out , 1.6mhz, synchronous boost dc/dc converter with adjustable input current limit 94% efficiency, v in : 1.8v to 5.5v, v out(max) = 5.25v, i q = 15a, i sd < 1a, 2mm 3mm dfn-8 package v in 1.8v to 5.5v 1.5a 10f 3.3h 301k 1.0m v out = 2.5v 220pf to load 100f 10f sw1 rsenp rsens run pfi pfo pgood maxv gnd fb prog mid ltc3128 sw2 v outp v outs v in 3128 ta01 7.32k 10f single output capacitor application (1.5a programmed input current) ? linear technology corporation 2014 lt 0314 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3128 ltc3128 3128f for more information www.linear.com/ltc3128

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